1. Field of the Invention
The present invention relates generally to interruptible computer systems, and more specifically to an interrupt controller for ARM and THUMB interrupt service routine switching, and that provide an interrupt-disable control bit.
2. Description of the Prior Art
Interrupt mechanisms in microprocessors allow input/output (I/O) and other peripheral controllers to request immediate service. This is more efficient than routinely checking with all such requesters to see if they need service. Interrupt controllers allow several interrupt sources to be prioritized and/or masked. One type of prior art interrupt controller jammed processor instructions on the databus that the processor was expected to execute. Other conventional priority interrupt controllers can cause a processor to branch unconditionally to a reserved section of main memory, e.g., a vector table. Each interrupt level will unconditionally branch the processor to a corresponding part of the vector table. From there, an interrupt service routine (ISR) can be executed that is customized for the particular interrupt priority level.
The ARM7TDMI is a highly popular and broadly licensed synthesizable 32-bit RISC microcontroller core. The “T” in TDMI refers to the so-called “Thumb” 16-bit RISC instruction set execution, the “D” refers to boundary-scan cell arrays for hardware debugging, the “M” refers to a built-in 32-bit arithmetic multiplier, and the “I” refers to an embedded in-circuit emulation (ICE) breaker cell provided for software debugging.
One of the key features of the ARM7TDMI microcontroller is its ability to run two instruction sets, e.g., ARM 32-bit instructions, and Thumb 16-bit instructions. The Thumb instructions are essentially decompressed in real-time during execution into ARM instructions. Executing a “BX” instruction will cause a switch between the two instruction sets. Due to the idiosyncrasies of these instruction sets, a lot of program code space can be saved by running the processor in the Thumb mode. The ARM mode offers higher performance, but at a cost in code space usage.
When an interrupt request is first received, the ARM7TDMI processor will switch, by design, to ARM instruction execution. So if program code space needs to be saved, every ISR will begin with the ARM instructions needed to put the processor in Thumb mode, e.g., a sort of ISR preamble. Similarly, the ends of the ISR's are generally duplicates of one another. For example to return the processor to ARM instruction execution. When program code space is really tight, such duplications are too costly.